Throttling memory in response to an internal temperature of a memory device

ABSTRACT

Systems and methods of managing memory devices provide for reduced power consumption and better thermal management through enhanced memory throttling. In one embodiment a memory unit includes a memory device and a temperature measurement module coupled to the memory device. The temperature measurement device measures the internal temperature of the memory device. Memory throttling can therefore be implemented based on more accurate measurements and with a much shorter response time.

RELATED PATENT APPLICATION

This application is a continuation of U.S. patent application Ser. No. 12/495,510, filed on Jun. 30, 2009; which is a continuation of U.S. patent application Ser. No. 11/924,754, filed on Oct. 26, 2007 and issued on Jun. 30, 2009, as U.S. Pat. No. 7,553,075; which is a division of U.S. patent application Ser. No. 10/825,923, filed May 24, 2004, issued on Dec. 4, 2007, as U.S. Pat. No. 7,304,905, the entire contents of which are hereby incorporated by reference herein.

BACKGROUND

Technical Field

Embodiments of the present invention generally relate to memory devices. More particularly, embodiments relate to throttling memory in a computer system.

Discussion

While recent trends in the computer industry toward smaller computing platforms and greater functionality have been desirable to consumers, these trends have presented a number of challenges to computer system designers as well as manufacturers. For example, designing notebook personal computers (PCs), personal digital assistants (PDAs) and wireless “smart” phones can be quite difficult due to the small form factor of these systems and their susceptibility to component overheating. In particular, excessive temperatures can cause processors, memory devices and other components to operate at a less than optimum performance level. In some cases, overheating can cause device failure. Overheating can also cause safety concerns with regard to the surface temperature of the platform enclosure. In addition, the applications being designed for computer systems continue to demand an increasing amount of power, which has a direct effect on temperature. For example, 3D gaming applications and “always-on” wireless features are just a sampling of the types of relatively high power applications available to consumers. When such applications are incorporated into small form factor computer systems, thermal concerns increase even more.

To better manage the above-described concerns, many computer designers establish a thermal design power (TDP) limit for a given platform, where the TDP essentially defines a power threshold that the platform should operate below in order to minimize overheating-related performance losses and safety concerns. In particular, it has been determined that accesses to memory units such as system memory can contribute significantly to the power consumption of the overall system. To address this problem, some solutions involve incorporating a temperature sensor into a memory controller hub (MCH), where the MCH controls accesses to the memory unit over a memory bus. If the temperature of the MCH exceeds a pre-set value, the memory unit is “throttled” by reducing memory access traffic to the memory unit.

While the above-described approach has been suitable under certain circumstances, a number of difficulties remain. For example, the temperature measured within the MCH does not reflect the actual internal temperature of the memory unit. As a result, correlating the measured temperature to the actual temperature can be difficult and may result in inaccuracies. Furthermore, to offset the risk of inaccurate temperature measurement, many designs involve overly conservative temperature limits and are therefore associated with significant performance losses. Another difficulty with the conventional approach relates to response time. In particular, some memory devices such as synchronous dynamic random access memory (SDRAM) devices have relatively high current surge transients that may require immediate shutdown in cases of overheating. The relatively long response time of the conventional approach, however, may not be able to detect the overheating in time because the temperature is measured at the MCH.

BRIEF DESCRIPTION OF THE DRAWINGS

The various advantages of the embodiments of the present invention will become apparent to one skilled in the art by reading the following specification and appended claims, and by referencing the following drawings, in which:

FIG. 1 is a block diagram of an example of a memory unit according to one embodiment of the invention;

FIG. 2 is a block diagram of an example of a system according to one embodiment of the invention;

FIG. 3 is a block diagram of an example of a serial presence detect device according to one embodiment of the invention; and

FIG. 4 is a flowchart of an example of a method of managing a memory device according to one embodiment of the invention.

DETAILED DESCRIPTION

FIG. 1 shows a memory unit 10 that provides a number of advantages over conventional memory units. In particular, the memory unit 10 has a plurality of memory devices 12 (12 a-12 n) and a temperature measurement module 14 coupled to the memory devices 12. As will be discussed in greater below, the memory unit 10 may be a small outline dual inline memory module (SO-DIMM) of the type typically used in notebook personal computers (PCs). The memory unit 10 could also be a micro DIMM, or a full-size DIMM, more commonly used in desktop PCs. Furthermore, the memory devices 12 may be synchronous dynamic random access memory (SDRAM) devices, which have relatively high current surge transients and can therefore be highly susceptible to overheating. While a number of the examples will be described with respect to SO-DIMMs and SDRAM devices, the embodiments of the invention are not so limited. Indeed, any memory device having temperature dependent performance can be used without parting from the nature and spirit of the embodiments described. Notwithstanding, there are a number of aspects of SO-DIMMs and SDRAM devices for which the principles described herein are well suited.

The illustrated temperature measurement module 14 measures an internal temperature of each of the memory devices 12. By measuring the internal temperature of the memory devices 12 rather than the internal temperature of a neighboring memory controller hub (MCH, not shown), the temperature measurement module 14 significantly obviates conventional concerns over accuracy and response time. For example, temperature measurements made by the module 14 more accurately reflect the die temperature of the memory devices 12, and can be used to detect overheating much more quickly than conventional temperature measurements.

Turning now to FIG. 2, one example of a system with an improved memory unit is shown in greater detail at 16. In particular, the system 16 includes a SO-DIMM 10′, an MCH 22, a system management interface 26 and a system memory bus 24. The SO-DIMM 10′ can have a 144-pin configuration that supports 64-bit transfers, a 72-pin configuration that supports 64-bit transfers, or any other acceptable configuration (see e.g., PC133 SDRAM Unbuffered SO-DIMM, Reference Design Specification, Version 1.02, JEDEC Standard No. 21-C, October, 2003). The illustrated SO-DIMM 10′ has a plurality of SDRAM devices 12′ (12 a′-12 d′) and a temperature measurement module 14′. While four SDRAM devices have been shown, a greater or smaller number of memory devices may be used. The temperature measurement module 14′ includes a serial presence detect (SPD) device 18 and a plurality of thermal diodes 20 (20 a-20 d), where each of the thermal diodes 20 is embedded in one of the SDRAM devices 12′.

In addition to storing configuration information (e.g., module size, data width, speed and voltage) used by the basic input/output system (BIOS, not shown) at system start-up, the SPD device 18 is able to transfer internal temperatures of the SDRAM devices 12′ to the system management interface 26. The system management interface 26 can generate throttling control signals if the internal temperatures exceed the temperature threshold, where the MCH 22 can reduce memory access traffic to (i.e., throttle) the SO-DIMM 10′ in response to the throttling control signals.

In particular, the illustrated system management interface 26 includes a system management bus 28 coupled to the SPD device 18 and a system controller (e.g., system management controller and keyboard controller, SMC/KBC) 30 coupled to the system management bus 28. The system controller 30 receives the internal temperatures from the SPD device 18 over the system management bus 28, compares the internal temperatures to the temperature threshold and generates the throttling control signals if the internal temperatures exceed the temperature threshold.

In one example, the system management bus 28 is an inter integrated circuit (I²C) bus (e.g., I²C Specification, Version 2.1, Phillips Semiconductors, January 2000), which can physically consist of two active wires and a ground connection. The active wires, termed serial data line (SDA) and serial clock line (SCL) are both bidirectional. In such an approach, each component connected to the bus can act as a receiver and/or transmitter depending on its functionality. In any given transaction, the component acting as a transmitter is considered the bus master and the remaining components are regarded as bus slaves. Thus, the SPD device 18 can function as a bus master and the system controller 30 can function as a bus slave with regard to the transfer of the internal temperatures. In cases where configuration information is being retrieved from an SPD electrically erasable programmable read only memory (EEPROM, not shown) for BIOS purposes, the system controller 30 may act as the bus master and the SPD device 18 may function as the bus slave.

The system management bus 28 can also operate under an SMBus framework (e.g., SMBus Specification, Version 2.0, SBS Implementers Forum, August 200). An SMBus interface uses I²C as its backbone, and enables components to pass messages back and forth rather than merely tripping individual control lines. Such an approach is particularly useful for memory units such as the SO-DIMM 10′, which transfers SPD data to BIOS.

The illustrated system management interface 26 also includes a chipset bus (e.g., Intel® low pin count/LPC Interface Specification, Rev. 1.1, August 2002) 32 coupled to the system controller 30, an input/output controller hub (ICH) 34 coupled the chipset bus 32 and a hub interface 36 coupled to the ICH 34 and the MCH 22. The ICH receives the throttling control signals from the system controller 30 over the chipset bus 32 and forwards the control signals to the MCH 22 over the hub interface 36. As already noted, the MCH 22 is able to throttle the SO-DIMM 10′ based on the control signals. In this regard, the system 16 may include other components (not shown) such as processors, graphics controllers, network interfaces, etc., that desire read and/or write access to the SDRAM devices 12′ on the SO-DIMM 10′ by way of the system memory bus 24 and/or MCH 22.

For example, a graphics controller could be processing a 3-dimensional (3D) gaming application that requires frequent accesses to one or more of the SDRAM devices 12′ over the system memory bus 24, where the MCH 22 has the ability to modulate traffic on the system memory bus 24. If the increased activity of the SDRAM devices 12′ results in an internal temperature of the SDRAM devices 12′ that is above a particular threshold, the system controller 30 generates a throttling initiation signal, which ultimately causes the MCH 22 to restrict memory access traffic on the system memory bus 24. By measuring the more accurate internal temperatures of the SDRAM devices 12′, the system 16 is able to implement more aggressive memory throttling. Furthermore, the system 16 is able to react to temperature spikes much more quickly than conventional systems.

Turning now to FIG. 3, one approach to implementing temperature measurement in an SPD device is shown in greater detail at 18′. In particular, the illustrated SPD device 18′ includes a current source 38 that injects a pair of measurement signals into each of the thermal diodes 20 (FIG. 2), where the measurement signals result in a temperature dependent voltage differential for each thermal diode. While the current source 38 is shown as being part of the SPD device 18′, the current source may also be located elsewhere in the system. Essentially, a first measurement signal having a known current is injected into a given thermal diode, where the first measurement signal results in a first voltage drop across the thermal diode. A second measurement signal also having a known current is then injected into the thermal diode, resulting in a second voltage drop. Since the forward bias current of the thermal diodes is a function of die temperature, the difference between the two voltage drops is also a function of die temperature. For example, the difference may be greater at high die temperatures than at low temperatures. The voltage across the thermal diode for the two measurement signals therefore defines a temperature dependent voltage differential. It should be noted that alternatively, a single measurement signal could be used to obtain an absolute voltage value. Due to the variation in voltage/current characteristics across thermal diodes, however, calibration may be needed to obtain an acceptable level of accuracy under such an approach.

The illustrated SPD device 18′ also has a multiplexer 40, which selects between the thermal diodes based on a selection signal from control logic 42. Selection can be in a “round-robin” fashion, or based on some other parameter such as memory device usage. In response to the selection signal, the multiplexer 40 connects the current source 38 to one of a pair of ports. For example, the control logic 42 can signal the multiplexer 40 to select ports DP1 and DN1, which may correspond to the anode and cathode terminals of thermal diode 20 a (FIG. 2), respectively. The control logic 42 then causes the current source 38 to inject the first measurement signal into port DP1. The voltage between port DP1 and port DN1 therefore represents the voltage drop across the thermal diode. The control logic 42 then causes the current source 38 to inject the second measurement signal into port DP1, resulting in a second voltage drop across the thermal diode. The difference between the two voltage drops (e.g., the temperature dependant voltage differential), which can be directly related to the temperature of the thermal diode, is sent to an analog to digital converter (ADC) 44.

In practice, additional circuitry may be used. For example, a low pass filter can be used to remove noise from the differential waveform and a chopper stabilized amplifier can be used to amplify and rectify the differential waveform to produce a direct current (DC) voltage proportional to the differential. Such circuitry has not been illustrated so as not to obscure more relevant aspects of the embodiments of the invention.

The ADC 44 can convert the temperature dependant voltage differential into a digital signal. Thus, each DP port can function as a combined current source and ADC positive input for a thermal diode channel, and each DN port can function as a combined current sink and ADC negative input. The control logic 42 may then proceed to the next pair of ports and the process is repeated. The illustrated SPD device 18′ also has a temperature calculation circuit 46 coupled to the ADC 44 to calculate the internal temperatures of the memory devices based on the digital signals.

Turning now to FIG. 4, a method 48 of managing a memory device is shown. The method 48 can be implemented in a memory unit using any appropriate hardware and/or software programming technique. For example, the method 48 could be readily incorporated into an application specific integrated circuit (ASIC) of a serial presence detect (SPD) device and/or system controller. Alternatively, the method 48 can be implemented as a set of instructions to be stored in a machine readable memory such as RAM, ROM, flash memory, and so on. The illustrated method 48 provides for injecting a pair of measurement signals into a thermal diode embedded within a memory device at processing block 50. The measurement signals result in a temperature dependent voltage differential for the thermal diode. Block 52 provides for converting the voltage differential into a digital signal and block 54 provides for calculating an internal temperature of the memory device based on the digital signal. The internal temperature is compared to a temperature threshold at block 56, and block 58 provides for determining whether the threshold has been exceeded. If so, a throttling control signal is issued to a memory controller hub at block 60. Otherwise, the next memory device is selected at block 62 and the process is repeated.

Thus, the techniques described herein can be used to significantly improve memory throttling and thermal design power in systems such as servers, desktop PCs, notebook PCs, personal digital assistants (PDAs), wireless “smart” phones, and so on. In particular, the small form factors associated with notebook PCs, PDAs and smart phones particularly lend themselves to the embodiments of the invention. Furthermore, memory structures having relatively high current surge transients that may require immediate shutdown in cases of overheating, can benefit considerably from the principles discussed.

The term “coupled” is used herein to refer to any type of connection, direct or indirect, that enables communication to take place across the interface in question. Thus, coupling might include intermediate components. The coupling might also provide for electronic, electromagnetic, optic and other forms of communication.

Those skilled in the art can appreciate from the foregoing description that the broad techniques of the embodiments of the present invention can be implemented in a variety of forms. Therefore, while the embodiments of this invention have been described in connection with particular examples thereof, the true scope of the embodiments of the invention should not be so limited since other modifications will become apparent to the skilled practitioner upon a study of the drawings, specification, and following claims. 

What is claimed is:
 1. An apparatus, comprising: a temperature measurement logic coupled to a memory module to receive temperature data corresponding to a temperature at a location of at least one memory device on the memory module; and in response to the temperature information indicating the temperature at the location exceeds a threshold, issue a signal, wherein the temperature measurement logic at least partially comprises an integrated circuit that includes a serial presence detect (SPD) electrically erasable programmable read only memory (EEPROM) having a current source that injects a pair of measurement signals into each of a pair of thermal diodes embedded within the memory module, the measurement signals result in a temperature dependent voltage differential for each thermal diode, and the SPD EEPROM provides one or more additional memory module functions apart from temperature measurement.
 2. The apparatus of claim 1, wherein the temperature measurement logic is communicatively coupled to at least an I2C bus master through an inter integrated circuit (I2C) bus.
 3. The apparatus of claim 2, wherein the temperature measurement logic to provide the received temperature data to an I2C bus master in response to a request from the I2C bus master.
 4. The apparatus of claim 2, wherein the temperature measurement logic comprises a slave on the I2C bus at least when in response to a read or write operation initiated by an I2C bus master.
 5. The apparatus of claim 1, wherein the temperature measurement logic repeatedly receives new temperature information.
 6. The apparatus of claim 1, wherein the memory module comprises a dynamic random access memory (DRAM) memory module.
 7. The apparatus of claim 1, further comprising a temperature sensor, wherein the temperature sensor to provide the temperature data to the temperature measurement control logic, and wherein the temperature sensor to be coupled to a memory device on the memory module.
 8. A memory module, comprising: one or more memory devices; and a temperature measurement logic coupled to a memory module to receive temperature data corresponding to a temperature at a location of at least one memory device on the memory module; and in response to the temperature information indicating the temperature at the location exceeds a threshold, issue a signal, wherein the temperature measurement logic at least partially comprises an integrated circuit that includes a serial presence detect (SPD) electrically erasable programmable read only memory (EEPROM) having a current source that injects a pair of measurement signals into each of a pair of thermal diodes embedded within the memory module, the measurement signals result in a temperature dependent voltage differential for each thermal diode, and the SPD EEPROM provides one or more additional memory module functions apart from temperature measurement.
 9. The memory module of claim 8, wherein the temperature measurement logic repeatedly receives new temperature information.
 10. The memory module of claim 8, wherein the memory module comprises a dynamic random access memory (DRAM) memory module.
 11. The memory module of claim 8, further comprising a temperature sensor, wherein the temperature sensor to provide the temperature data to the temperature measurement control logic, and wherein the temperature sensor to be coupled to a memory device on the memory module.
 12. The memory module of claim 8, wherein the temperature measurement logic is communicatively coupled to at least an I2C bus master through an inter integrated circuit (I2C) bus.
 13. The memory module of claim 12, wherein the temperature measurement logic to provide the received temperature data to an I2C bus master in response to a request from the I2C bus master.
 14. The memory module of claim 12, wherein the temperature measurement logic comprises a slave on the I2C bus at least when in response to a read or write operation initiated by an I2C bus master. 